1. Field of the Invention
This invention relates generally to the field of semiconductor memory and logic devices. The invention relates more specifically to a silicon-on-insulator structure, and a method of fabrication therefor.
2. Description of the Related Art
In the field of microelectronics, SOI (Silicon-on-Insulator)-CMOS technology has been demonstrated to have significant speed, power, and radiation immunity advantages over bulk CMOS technology. See, e.g., “Scalability of SOI Technology into 0.13 um 1.2 V CMOS Generation,” E. Leobandung, et al., IEDM, 1998, pp. 403-406, and “SOI and Device Scaling,” C. Hu, Proceedings of IEEE International SOI Conference, Oct. 1998, pp. 1-4.
SOI-CMOS technology, however, has yet to be widely accepted by the systems and circuit design communities because of the complexity of managing an anomalous effect termed the “floating body effect” (hereinafter “FBE”), of the SOI devices, and in particular, of NFET-SOI devices. Unlike bulk NMOSFET devices, in which the body is tied to either a fixed potential or to the source of the device, body potential in NMOSFET-SOI devices is floating, and remains unstable due to the complex dynamics of both positive-charge carrier, or “hole,” generation by impact ionization at the drain edge, and by recombination and diffusion. As a result of this floating potential, NMOSFET-SOI devices exhibit several undesirable characteristics, such as a “kink effect” (current enhancement) in the Id-Vg characteristics of the device, enhanced leakage attributable to parasitic (npn) bipolar junction transistor (BJT) current, and enhanced 1/f noise. In addition, circuit-related drawbacks attributable to FBE include threshold instability, hysterectic behavior in signal input/output, frequency dependent pulse delays, and signal pulse width modulation. The parasitic bipolar current adversely affects memory sense and write operations (in SRAM memory) as well as data retention (in SDRAM memory). “SOI Floating Body, Devices, and Circuit Issues,” J. Cautier, et al., IEDM, 1997, pp. 407-410.
In logic design, such drawbacks can lead to data loss and dynamic circuit failure, as well as timing delays. Additionally, analog circuit applications may be seriously limited due to transistor mismatch and enhanced AC/DC noise. Therefore, overcoming FBE is a major obstacle to the widespread application of SOI-CMOS.
Several solutions have been proposed to suppress FBE. For example, with field shield isolation technology, FBE has been minimized for SOI-NFET gate arrays by using a field shielded gate and by collecting excess holes via the body contact under the field shield. “CAD-Compatible High-Speed CMOS/SIMOX Gate Array Using Field-Shield Isolation,” T. Iwamatsu, et al., IEEE Trans. Elec. Devices, Vol. 42, No. 11, 1995, pp. 1934-1938. In addition, by using a field shielded gate, it has been demonstrated that delay time instability of logic circuits can be suppressed over a particular frequency range. “Suppression of Delay Time Instability on Frequency Using Field Shield Isolation Technology for Deep Submicron SOI Circuits,” S. Maeda, et al., IEDM, 1996, pp. 129-132.
In another approach, a bipolar embedded source structure (BESS) has been employed to suppress FBE. “BESS: A Source Structure that Fully Suppresses the Floating Body Effects in SOI CMOSFETs,” M. Horiuchi, et al., IEDM 1996, pp. 121-124. In the BESS approach, FBE is suppressed by creating a recombination region (collector) for holes and by shunting the holes via a low built-in potential barrier region (n-base). The structure is created below the n+ source region between the SOI/BOX (buried oxide) interface, whereby the p-type body of the SOI-NFET acts as the source of holes (i.e., an emitter). The BESS approach has been shown to suppress FBE and improve DIBL (drain induced barrier lowering), an undesirable device characteristic.
In still another approach, using a Si—Ge inserted SOI, a graded thin layer of Si—Ge is epitaxially inserted into a p-type silicon body toward its bottom, close to the BOX region. “A Novel Si—Ge Inserted SOI Structure for High Performance PDSOI CMOSFET,” G. T. Bae, et al, IEDM, 2000, pp. 667-670. This creates a narrow band gap region (the band gap of Ge is 0.66 ev compared to a band gap of 1.12 ev for Si) in the body and lowers body-source potential barrier to hole current without affecting the FET channel characteristics. As a result, the parasitic bipolar current gain is reduced, and hole recombination at the n+Si—Ge (source-element)/p-Si—Ge (body element) region is enhanced.
In each of the above-described prior art approaches to overcoming FBE, the central theme is to facilitate the recombination of the excess holes generated by impact ionization. That is, the objective is for the excess holes to be swept away and recombined by a mechanism (or combination of mechanisms) that yields a very small (i.e., a short, or faster) recombination time constant. If a very small time constant could be achieved, the body (e.g., the base of a parasitic BJT bipolar device) would never be charged sufficiently so as to trigger bipolar action. If such a dynamic equilibrium could be achieved for generation and recombination of holes, the body would maintain a constant low body potential regardless of the time constant and the mechanism of hole generation. Consequently, large hole generation would lead to a large recombination current and, therefore, a low gain (i.e., large base current) for a parasitic bipolar device. The resulting device would not exhibit a greater drain induced barrier lowering effect, and would not have reduced source to drain breakdown. Furthermore, circuits employed would not exhibit any hysteretic effects regardless of pulse frequency, or any excessive pass-gate leakage, or any data loss or pulse width modulation.
Therefore, a need exists for a solution to the floating body effect that can be achieved at the minimum increase in process complexity and the minimum impact on device density and other required device characteristics, such as device current, desired device leakage, and capacitance.